{"id":2677,"date":"2026-07-12T15:55:30","date_gmt":"2026-07-12T15:55:30","guid":{"rendered":"https:\/\/mvermeulen.org\/perf\/?p=2677"},"modified":"2026-07-12T15:55:32","modified_gmt":"2026-07-12T15:55:32","slug":"arm-box-inventory-script","status":"publish","type":"post","link":"https:\/\/mvermeulen.org\/perf\/2026\/07\/12\/arm-box-inventory-script\/","title":{"rendered":"ARM box, inventory script"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">I have a Minisforum <a href=\"https:\/\/www.minisforum.com\/products\/ms-r1\">MS-R1<\/a> system that will let me experiment further with Aarch 64 cores on Linux. To help me with this discovery, I extended several scripts to inventory and examine the system so will also show those scripts outputs on this system and others to calibrate.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The first script generates the topology of both cores and cache on the system from \/sys entries:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>================================================================================\nCPU CORE &amp; CACHE HIERARCHY MAP (AARCH64)\n================================================================================\nTotal Cores: 12\n\nCore Details Table:\nCore   Core Model                   Stepping   Max Freq     L1I\/L1D Cache    L2 Cache  \n----------------------------------------------------------------------------------------\ncpu0   ARM Cortex-A720              r0p1       2600 MHz     64K \/ 64K        512K      \ncpu1   ARM Cortex-A720              r0p1       2600 MHz     64K \/ 64K        512K      \ncpu2   ARM Cortex-A520              r0p1       1800 MHz     32K \/ 32K        N\/A       \ncpu3   ARM Cortex-A520              r0p1       1800 MHz     32K \/ 32K        N\/A       \ncpu4   ARM Cortex-A520              r0p1       1800 MHz     32K \/ 32K        N\/A       \ncpu5   ARM Cortex-A520              r0p1       1800 MHz     32K \/ 32K        N\/A       \ncpu6   ARM Cortex-A720              r0p1       2300 MHz     64K \/ 64K        512K      \ncpu7   ARM Cortex-A720              r0p1       2300 MHz     64K \/ 64K        512K      \ncpu8   ARM Cortex-A720              r0p1       2200 MHz     64K \/ 64K        512K      \ncpu9   ARM Cortex-A720              r0p1       2200 MHz     64K \/ 64K        512K      \ncpu10  ARM Cortex-A720              r0p1       2500 MHz     64K \/ 64K        512K      \ncpu11  ARM Cortex-A720              r0p1       2500 MHz     64K \/ 64K        512K      \n\nSystem-wide Cache Capacity Summary:\n - L1 Data        Cache: 640 KiB      (Total across 4x 32K, 8x 64K)\n - L1 Instruction Cache: 640 KiB      (Total across 4x 32K, 8x 64K)\n - L2 Unified     Cache: 4.0 MiB      (Total across 8x 512K, 4x unreported)\n - L3 Unified     Cache: 12.0 MiB     (Total across 1x 12288K)\n\n================================================================================\nTOPOLOGY PLUMBING TREE\n================================================================================\nL3 Unified Cache &#91;12288K]\n\u251c\u2500\u2500 Core 11: ARM Cortex-A720 (r0p1) @ 2.50 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 10: ARM Cortex-A720 (r0p1) @ 2.50 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 9: ARM Cortex-A720 (r0p1) @ 2.20 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 8: ARM Cortex-A720 (r0p1) @ 2.20 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 7: ARM Cortex-A720 (r0p1) @ 2.30 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 6: ARM Cortex-A720 (r0p1) @ 2.30 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u251c\u2500\u2500 Core 5: ARM Cortex-A520 (r0p1) @ 1.80 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (32K), L1 Instruction (32K)\n\u251c\u2500\u2500 Core 4: ARM Cortex-A520 (r0p1) @ 1.80 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (32K), L1 Instruction (32K)\n\u251c\u2500\u2500 Core 3: ARM Cortex-A520 (r0p1) @ 1.80 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (32K), L1 Instruction (32K)\n\u251c\u2500\u2500 Core 2: ARM Cortex-A520 (r0p1) @ 1.80 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (32K), L1 Instruction (32K)\n\u251c\u2500\u2500 Core 1: ARM Cortex-A720 (r0p1) @ 2.60 GHz\n\u2502   \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n\u2514\u2500\u2500 Core 0: ARM Cortex-A720 (r0p1) @ 2.60 GHz\n    \u2514\u2500 Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)\n<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">This shows this SOC has a mix of both Cortex A720 cores and Cortex A520 cores and even the Cortex A720 cores have different maximum frequencies reflecting possible different between &#8220;high&#8221; and &#8220;mid&#8221; cores.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The first thing we do on this new system is run a sweep of stream pinned to different cores. I updated a script to consider the core capability, the optimization level and the number of threads to create the following measurements:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>triad_MBps\topt_level\tthreads\tstrategy\tdomain\tcpus\trun\n39170.300000\tO2\t4\tlocal_l3\t0\t0,1,10,11\t1\n38441.200000\tO2\t2\tlocal_l3\t0\t0,1\t1\n37068.000000\tO2\t2\tlocal_l3_cc\t0\t0,10\t1\n36531.400000\tO2\t3\tlocal_l3\t0\t0,1,10\t1\n35612.500000\tO2\t2\tlocal_l3_cc\t0\t0,6\t1\n34266.600000\tO2\t2\tlocal_l3_cc\t0\t0,11\t1\n33733.900000\tO2\t2\tlocal_l3_cc\t0\t0,7\t1\n26004.700000\tO2\t1\tlocal_l3\t0\t0\t1\n<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">The highest stream triad comes from running four threads and pinning to the four highest frequency Cortex 720 cores. Just using the two fastest cores comes close.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The next thing we do is try coremark for each individual core<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>cpu\trun\tstatus\tcoremark_average\tlog_file\n0\t1\tOK\t25512.373511\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu0.run1.txt\n1\t1\tOK\t25511.108133\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu1.run1.txt\n2\t1\tOK\t8182.294456\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu2.run1.txt\n3\t1\tOK\t8168.957901\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu3.run1.txt\n4\t1\tOK\t8172.910173\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu4.run1.txt\n5\t1\tOK\t8176.058957\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu5.run1.txt\n6\t1\tOK\t22462.563490\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu6.run1.txt\n7\t1\tOK\t22442.589501\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu7.run1.txt\n8\t1\tOK\t21470.071023\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu8.run1.txt\n9\t1\tOK\t21462.437238\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu9.run1.txt\n10\t1\tOK\t24509.139361\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu10.run1.txt\n11\t1\tOK\t24504.245930\t\/home\/mev\/source\/perf\/results\/coremark_each_core\/coremark.cpu11.run1.txt\n<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">This shows us results that are consistent with the cores and their maximum frequencies. It surprises me how much quicker a Cortex 720 is than a Cortex 520, so some strategy that pins to the 8 Cortex 720 cores might make sense in some situations.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>coremark_average\tscenario\tdomain\tthreads\tcpus\trun\n172518.777163\tthread0_only\tall\t12\t0,1,2,3,4,5,6,7,8,9,10,11\t1\n168110.086124\tall_logical\tall\t12\t0,1,2,3,4,5,6,7,8,9,10,11\t1\n51064.558269\tcapability_group\t0\t2\t0,1\t1\n49082.209232\tcapability_group\t1\t2\t10,11\t1\n44976.394529\tcapability_group\t2\t2\t6,7\t1\n43020.862299\tcapability_group\t3\t2\t8,9\t1\n33342.065373\tcapability_group\t4\t4\t2,3,4,5\t1\n<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">I also tried some aggregation of running on all cores, on all thread 0 (hyperthread) and for each pair of cores that have the same capabilities. The first two numbers are close because they are the same run. The pairs of Cortex cores by themselves have coremark scores according to frequencies. The four Cortex 520 cores by themselves are slower than any pair of Cortex 720 cores.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">As a follow on post, I will also document what these same scripts have shown with a Ryzen AI 9 370 also show.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I have a Minisforum MS-R1 system that will let me experiment further with Aarch 64 cores on Linux. To help me with this discovery, I extended several scripts to inventory and examine the system so will also show those scripts <span class=\"excerpt-dots\">&hellip;<\/span> <a class=\"more-link\" href=\"https:\/\/mvermeulen.org\/perf\/2026\/07\/12\/arm-box-inventory-script\/\"><span class=\"more-msg\">Continue reading &rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[11,9,5],"tags":[43,38,10],"class_list":["post-2677","post","type-post","status-publish","format-standard","hentry","category-experiment","category-hardware","category-tools","tag-aarch64","tag-coremark","tag-stream"],"_links":{"self":[{"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/posts\/2677","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/comments?post=2677"}],"version-history":[{"count":2,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/posts\/2677\/revisions"}],"predecessor-version":[{"id":2680,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/posts\/2677\/revisions\/2680"}],"wp:attachment":[{"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/media?parent=2677"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/categories?post=2677"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mvermeulen.org\/perf\/wp-json\/wp\/v2\/tags?post=2677"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}