Performance Counters required to compute topdown metrics
From past work, we know the five counters required to compute the first level topdown metrics on Intel processors:
CLK_UNHALTED_CORE = 0x00 IDQ_UOPS_NOT_DELIVERED_CORE = 0x9C, umask=1 UOPS_RETIRED_RETIRE_SLOTS = 0xC2, umask=2 UOPS_ISSUED_ANY = 0x0E, umask=1 INT_MISC_RECOVERY_CYCLES = 0x0d, umask=3, cmask=1
These can be composed as follows
width = 4 ; issue width = 4 for many processors total-slots = CLK_UNHALTED_CORE * width frontend = IDQ_UOPS_NOT_DELIVERED_CORE / total-slots retiring = UOPS_RETIRED_RETIRE_SLOTS / total-slots speculation = (UOPS_ISSUED_ANY - UOPS_RETIRED_RETIRE_SLOTS + (width*INT_MISC_RECOVERY_CYCLES)/width backend = 1 - (frontend + retiring + speculation)
Now working with the definitions from “perf-list” we can also find the set of performance counters used to compute topdown metrics on AMD. First here are the definitions that perf gives us:
PipelineL1:
backend_bound
[d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)]
bad_speculation
[d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)]
frontend_bound
[d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend,
total_dispatch_slots)]
retiring
[d_ratio(ex_ret_ops, total_dispatch_slots)]
smt_contention
[d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)]
This simplifies further
de_no_dispatch_per_slot.backend_stalls = 0x1A, umask=0x1E total_dispatch_slots = 6 * ls_not_halted_cyc ls_not_halted_cyc = 0x76 de_src_op_disp.all = 0xAA, umask=0x7 ex_ret_ops = 0xC1 de_no_dispatch_per_slots.no_ops_from_frontend = 0x1A0, umask=1 de_no_dispatch_per_slot.smt_contention = 0x1A0, umask=0x60
So I believe we can compute top-down metrics using six counters listed above and then also have an additional category to account for pipeline slots not dispatched because of SMT contention.

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