I have a Minisforum MS-R1 system that will let me experiment further with Aarch 64 cores on Linux. To help me with this discovery, I extended several scripts to inventory and examine the system so will also show those scripts outputs on this system and others to calibrate.
The first script generates the topology of both cores and cache on the system from /sys entries:
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CPU CORE & CACHE HIERARCHY MAP (AARCH64)
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Total Cores: 12
Core Details Table:
Core Core Model Stepping Max Freq L1I/L1D Cache L2 Cache
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cpu0 ARM Cortex-A720 r0p1 2600 MHz 64K / 64K 512K
cpu1 ARM Cortex-A720 r0p1 2600 MHz 64K / 64K 512K
cpu2 ARM Cortex-A520 r0p1 1800 MHz 32K / 32K N/A
cpu3 ARM Cortex-A520 r0p1 1800 MHz 32K / 32K N/A
cpu4 ARM Cortex-A520 r0p1 1800 MHz 32K / 32K N/A
cpu5 ARM Cortex-A520 r0p1 1800 MHz 32K / 32K N/A
cpu6 ARM Cortex-A720 r0p1 2300 MHz 64K / 64K 512K
cpu7 ARM Cortex-A720 r0p1 2300 MHz 64K / 64K 512K
cpu8 ARM Cortex-A720 r0p1 2200 MHz 64K / 64K 512K
cpu9 ARM Cortex-A720 r0p1 2200 MHz 64K / 64K 512K
cpu10 ARM Cortex-A720 r0p1 2500 MHz 64K / 64K 512K
cpu11 ARM Cortex-A720 r0p1 2500 MHz 64K / 64K 512K
System-wide Cache Capacity Summary:
- L1 Data Cache: 640 KiB (Total across 4x 32K, 8x 64K)
- L1 Instruction Cache: 640 KiB (Total across 4x 32K, 8x 64K)
- L2 Unified Cache: 4.0 MiB (Total across 8x 512K, 4x unreported)
- L3 Unified Cache: 12.0 MiB (Total across 1x 12288K)
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TOPOLOGY PLUMBING TREE
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L3 Unified Cache [12288K]
├── Core 11: ARM Cortex-A720 (r0p1) @ 2.50 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 10: ARM Cortex-A720 (r0p1) @ 2.50 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 9: ARM Cortex-A720 (r0p1) @ 2.20 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 8: ARM Cortex-A720 (r0p1) @ 2.20 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 7: ARM Cortex-A720 (r0p1) @ 2.30 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 6: ARM Cortex-A720 (r0p1) @ 2.30 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
├── Core 5: ARM Cortex-A520 (r0p1) @ 1.80 GHz
│ └─ Private Caches: L1 Data (32K), L1 Instruction (32K)
├── Core 4: ARM Cortex-A520 (r0p1) @ 1.80 GHz
│ └─ Private Caches: L1 Data (32K), L1 Instruction (32K)
├── Core 3: ARM Cortex-A520 (r0p1) @ 1.80 GHz
│ └─ Private Caches: L1 Data (32K), L1 Instruction (32K)
├── Core 2: ARM Cortex-A520 (r0p1) @ 1.80 GHz
│ └─ Private Caches: L1 Data (32K), L1 Instruction (32K)
├── Core 1: ARM Cortex-A720 (r0p1) @ 2.60 GHz
│ └─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
└── Core 0: ARM Cortex-A720 (r0p1) @ 2.60 GHz
└─ Private Caches: L1 Data (64K), L1 Instruction (64K), L2 Unified (512K)
This shows this SOC has a mix of both Cortex A720 cores and Cortex A520 cores and even the Cortex A720 cores have different maximum frequencies reflecting possible different between “high” and “mid” cores.
The first thing we do on this new system is run a sweep of stream pinned to different cores. I updated a script to consider the core capability, the optimization level and the number of threads to create the following measurements:
triad_MBps opt_level threads strategy domain cpus run
39170.300000 O2 4 local_l3 0 0,1,10,11 1
38441.200000 O2 2 local_l3 0 0,1 1
37068.000000 O2 2 local_l3_cc 0 0,10 1
36531.400000 O2 3 local_l3 0 0,1,10 1
35612.500000 O2 2 local_l3_cc 0 0,6 1
34266.600000 O2 2 local_l3_cc 0 0,11 1
33733.900000 O2 2 local_l3_cc 0 0,7 1
26004.700000 O2 1 local_l3 0 0 1
The highest stream triad comes from running four threads and pinning to the four highest frequency Cortex 720 cores. Just using the two fastest cores comes close.
The next thing we do is try coremark for each individual core
cpu run status coremark_average log_file
0 1 OK 25512.373511 /home/mev/source/perf/results/coremark_each_core/coremark.cpu0.run1.txt
1 1 OK 25511.108133 /home/mev/source/perf/results/coremark_each_core/coremark.cpu1.run1.txt
2 1 OK 8182.294456 /home/mev/source/perf/results/coremark_each_core/coremark.cpu2.run1.txt
3 1 OK 8168.957901 /home/mev/source/perf/results/coremark_each_core/coremark.cpu3.run1.txt
4 1 OK 8172.910173 /home/mev/source/perf/results/coremark_each_core/coremark.cpu4.run1.txt
5 1 OK 8176.058957 /home/mev/source/perf/results/coremark_each_core/coremark.cpu5.run1.txt
6 1 OK 22462.563490 /home/mev/source/perf/results/coremark_each_core/coremark.cpu6.run1.txt
7 1 OK 22442.589501 /home/mev/source/perf/results/coremark_each_core/coremark.cpu7.run1.txt
8 1 OK 21470.071023 /home/mev/source/perf/results/coremark_each_core/coremark.cpu8.run1.txt
9 1 OK 21462.437238 /home/mev/source/perf/results/coremark_each_core/coremark.cpu9.run1.txt
10 1 OK 24509.139361 /home/mev/source/perf/results/coremark_each_core/coremark.cpu10.run1.txt
11 1 OK 24504.245930 /home/mev/source/perf/results/coremark_each_core/coremark.cpu11.run1.txt
This shows us results that are consistent with the cores and their maximum frequencies. It surprises me how much quicker a Cortex 720 is than a Cortex 520, so some strategy that pins to the 8 Cortex 720 cores might make sense in some situations.
coremark_average scenario domain threads cpus run
172518.777163 thread0_only all 12 0,1,2,3,4,5,6,7,8,9,10,11 1
168110.086124 all_logical all 12 0,1,2,3,4,5,6,7,8,9,10,11 1
51064.558269 capability_group 0 2 0,1 1
49082.209232 capability_group 1 2 10,11 1
44976.394529 capability_group 2 2 6,7 1
43020.862299 capability_group 3 2 8,9 1
33342.065373 capability_group 4 4 2,3,4,5 1
I also tried some aggregation of running on all cores, on all thread 0 (hyperthread) and for each pair of cores that have the same capabilities. The first two numbers are close because they are the same run. The pairs of Cortex cores by themselves have coremark scores according to frequencies. The four Cortex 520 cores by themselves are slower than any pair of Cortex 720 cores.
As a follow on post, I will also document what these same scripts have shown with a Ryzen AI 9 370 also show.
